The present invention disclosed herein relates to memory systems and, more particularly, to memory systems having a multilevel cell flash memory and programming methods thereof.
Portable apparatus that use nonvolatile memories are increasingly used today. Nonvolatile memories may be embedded as storage units in MP3 players, digital cameras, mobile phones, camcorders, flash cards, solid state disks (SSDs), and so on.
Increasing with apparatus that use nonvolatile memories as storage units, memory capacities thereof are increasing rapidly. One of the ways for increasing the memory capacity is a multi-level cell (MLC) mode that stores multiple bits in a unit memory cell.
FIG. 1 is a block diagram of a conventional memory system. Referring to FIG. 1, the memory system 100 includes a host 110, a memory controller 120, and a flash memory 130.
The memory controller 120 includes a buffer memory 121. The flash memory 130 includes a cell array 131 and a page buffer 132. Although not shown in FIG. 1, the flash memory 130 also includes a decoder, a data buffer, and a control unit.
The memory controller 120 receives data and a write command from the host 110, and controls the flash memory 130 to write the received data into the cell array 131. Further, the memory controller 120 operates to control the flash memory 130 to read data from the cell array 131 in compliance with a read command provided from the host 110.
The buffer memory 121 temporarily stores data to be written into or read from the flash memory 130. The buffer memory 121 transfers data, which are stored therein provisionally by the memory controller 120, to the host 110 or the flash memory 130.
The cell array 131 of the flash memory 130 is composed of a plurality of memory cells. These memory cells are nonvolatile, retaining their data even without power after storing the data. The page buffer 132 is provided to store data to be written into or data read from a selected page.
A memory cell of the flash memory 130 is classified into a single-level cell (SLC) type and a multi-level cell (MLC) type in accordance with the number of data bits able to be stored. The SLC stores single-bit data, while the MLC stores multi-bit data.
First, the memory considers an SLC mode in which a unit cell stores a single data bit. The SLC is operable in two states according to a distribution of threshold voltages. This SLC stores data ‘1’ or ‘0’ after a programming operation. Here, a memory cell storing data ‘1’ is referred to as being conditioned in an erased state, while a memory cell storing data ‘0’ is referred to as being conditioned in a programmed state. A memory cell of the erased state is called an ‘on-cell’, while a memory cell of the programmed state is called an ‘off-cell’.
The flash memory 130 conducts a programming operation in the unit of page. The memory controller 120 transfers data to the flash memory 130 through the buffer memory 121 in the unit of page during a programming operation.
The page buffer 132 temporarily stores data loaded from the buffer memory 121, and programs the loaded data into a selected page at the same time. After completing the programming operation, a program-verifying operation is carried out for verifying whether the data have been correctly programmed.
From a result of the program-verifying operation, if there is a program fail, program-verifying operations are repeated while incrementing a program voltage. After completely programming data corresponding to one page, the next data are received for the next programming operation.
Next, the memory considers an MLC mode in which a unit cell stores multi-bit data. FIG. 2 shows a conventional procedure of programming 2-bit data, i.e., a least significant bit (LB) and a not significant bit (MSB), into a single memory cell.
Referring to FIG. 2, a memory cell is programmed to have one of four states 11, 01, 10, and 00 in accordance with a distribution of threshold voltages. A procedure of programming an LSB is the same as that of the aforementioned SLC mode. A memory cell conditioned in the ‘11’ state is programmed to have a state A depicted by a dotted line in accordance with an LSB.
Then, the memory controller 120 transfers page data (data corresponding to one page) to the flash memory 130 from the buffer memory 121 to program an MSB. Referring to FIG. 2, a memory cell conditioned according to the dotted curve A is programmed to have the ‘00’ state (program1) or the ‘10’ state (program2). Meanwhile, a memory cell programmed to the ‘11’ state is maintained in the ‘11’ state or programmed to the ‘01’ state (program3) in accordance with an MSB.
Returning to FIG. 1, the memory system 100 programs multi-bit data into the cell array 131 of the flash memory 130 by way of the aforementioned procedure. Namely, multi-bit data are programmed by the successive steps of first programming an LSB and then programming an MSB into the memory cell that has been programmed with the LSB.
However, there is a probability of failure while programming an MSB into a memory cell that has been programmed with an LSB. If there is an error while programming an MSB, it would effect a change of the LSB already programmed.
As an MSB is stored in the buffer memory 121 of the memory controller 120 until completing a program-verifying operation, data may be restored although it is damaged. Because an LSB is not maintained in the buffer memory 121, there is no way of restoring the LSB. Thus, such a conventional memory system may lose its LSB inadvertently while programming multi-bit data.